Donald Thomas has written the book that sits between Digital Design 101 and UVM Reference Manual . It is the missing link.
Beyond the Schematic: Why Donald Thomas’ “Logic Design and Verification Using SystemVerilog” is a Modern Classic Donald Thomas has written the book that sits
9.5/10 (Deducted half a point because the index could be more thorough). Additionally, the revised edition is still light on
Additionally, the revised edition is still light on (Xilinx/Altera specific). This is a textbook for ASIC methodology, but 90% applies directly to high-end FPGAs. The Verdict: Buy it. Read it. Dog-ear it. If you are an early-career digital designer, Logic Design and Verification Using SystemVerilog (Revised) will cut your debug time in half. If you are a verification engineer, it will make you a better designer because you will finally understand why RTL engineers write "bad" code (and how to fix it). Read it