// Stage 2 full_adder fa1 ( .a(pp0[2]), .b(pp1[1]), .cin(c1), .sum(s1), .cout(c2) );
// Stage 4 full_adder fa4 ( .a(c4), .b(pp2[2]), .cin(s3), .sum(product[3]), .cout(c6) );
for most FPGA/ASIC designs unless you need explicit gate-level control for teaching or low-level optimization.
full_adder fa3 ( .a(s2), .b(pp2[1]), .cin(c3), .sum(s3), .cout(c5) );
// Half adder for LSB assign product[0] = pp0[0];
// Final stage assign product[5] = c5 | c6; // final carry out assign product[4] = (c5 ^ c6); // optional, adjust based on actual addition endmodule